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H.264 / MPEG4 Part 10 Main & High Profile Decoder

The Decoder core is a fully pipelined dedicated video compression engine capable of supporting the H.264/ AVC / MPEG4 Part 10 video standard. The core reads an input bit stream (and reference pictures) from external memory and outputs a decoded picture back to memory.  

Host processor requirements are minimal and only a few registers specifying the active sequence and picture parameter sets must be programmed at boot up. The core itself may be either fully or partially autonomous.The core requires a single external memory component. This component may be any of SRAM, SDRAM, DDR or DDR2 memory . The memory must be large enough to store the required number of reference frames. Typically 64bit SDR or 32 bit DDR is adequate.The memory bus and core are fully asynchronous and the memory core transfers can be carried out at the highest achievable memory clock speed for maximum efficiency. The core can also generally share this memory with the host or render components with no loss of performance.

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H.264 / MPEG4 Part 10 Baseline Video Encoder

The Encoder core is a fully pipelined dedicated video compression engine that implements the H.264 (baseline) encoding standard. The core reads a video frame from external memory and outputs an encoded bit stream (and decoded reference picture) back to memory.  

Host processor requirements are minimal and only a few registers (specifying the frame locations and coding options) need be programmed once at the beginning of each frame. This can be done either in HDL or by a sepaate processor requiring only a few MIPs.  

The core requires a single memory component, which may be any of SRAM, SDRAM, DDR or DDR2. If the memory is fast enough then the core can generally share this memory with other encoder cores and the host and capture components with no loss of performance.  

Several encoder cores may also be composed into a single core, capable of seamlessly encoding video at HDTV rates even in the slowest FPGA families. The encoder cores are also configurable at build time, with both the number of reference frames, and number of motion estimators per reference frame being configurable.

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H.261/3 Video Encoder and Decoder

H.261/3 Video encoder and decoder IP cores support real-time encoding and decoding of H.261/3 base-line compliant digital video streams. This flexible, fast implementation is ideal for videoconferencing and video transmission applications. Available in VHDL , the "IP" core is designed for rapid integration into your FPGA or ASIC-based system.

Features

  • VHDL design, suitable for synthesis to FPGA or ASIC.

  • Encoder requires just 3000 xilinx slices and 22KB RAM in Xilinx Virtex 2.

  • Encodes NTSC (704 x 480) at 30 fps 52 MHz, CIF 30 fps at 16 MHz, QCIF 15 fps at 2MHz.

  • 4-SIF operation requires 2 MBytes of single external RAM for frame buffers.

  • Default configuration supports MPEG-4 short header compliant video encoder and decoder with hardware VLC.

  • Option for software VLC to allow easy multi-standard support in a small core.

  • Option for hardware VLC to support short header MPEG4, simple profile MPEG4, JPEG, MPEG1, MPEG2, H.261 and H.263.

  • Can be supplied on FPGA evaluation board for the PC with evaluation software.

  • Efficient ASIC implementation (<40K gates) - requires no dedicated FPGA multipliers.

  • External processor only has to set 7 registers once per frame.

  • can demonstrate real-time 4-SIF 30 fps encoder/decoder operation with low latency RTP Internet streaming now.

  • can combine this encoder IP core with RTP streaming and our IPP optimised Win32 DirectShow software decoder. 

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MPEG4 Video Codec

MPEG4 Video encoder and decoder IP cores support real-time encoding and decoding of MPEG-4  compliant digital video streams. This flexible, fast implementation is ideal for videoconferencing and video transmission applications. Available in VHDL , the "IP" core is designed for rapid integration into your FPGA or ASIC-based system.

Features

  • VHDL design, suitable for synthesis to FPGA or ASIC.

  • Encoder requires just 3000 xilinx slices and 22KB RAM in Xilinx Virtex 2.

  • Encodes NTSC (704 x 480) at 30 fps 52 MHz, CIF 30 fps at 16 MHz, QCIF 15 fps at 2MHz.

  • 4-SIF operation requires 2 MBytes of single external RAM for frame buffers.

  • Default configuration supports MPEG-4 short header compliant video encoder and decoder with hardware VLC.

  • Option for software VLC to allow easy multi-standard support in a small core.

  • Option for hardware VLC to support short header MPEG4, simple profile MPEG4, JPEG, MPEG1, MPEG2, H.261 and H.263.

  • Can be supplied on FPGA evaluation board for the PC with evaluation software.

  • Efficient ASIC implementation (<40K gates) - requires no dedicated FPGA multipliers.

  • External processor only has to set 7 registers once per frame.

  • can demonstrate real-time 4-SIF 30 fps encoder/decoder operation with low latency RTP Internet streaming now.

  • can combine this encoder IP core with RTP streaming and our IPP optimised Win32 DirectShow software decoder. 

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MPEG4 Simple Profile Decoder

The MPEG-4 decoder is a hardware module optimized for FPGA technologies, making use of a limited number of logic resources and being able to decode a 4CIF (704x576) sequence in real time. The decoder can also be used to decode multiple streams simultaneously (up to 8).  

It is compliant with the Video part of ISO/IEC 14496-2. Most of the visual tools of the Simple Profile are implemented, including support of I-VOP (intra-coded frames, without motion estimation) and P-VOP (predictive-coded frame, with motion estimation on previously encoded frame).  

The following tools are supported:  

  • Half pixel motion
  • I-VOP, P-VOP

The following tools are not supported:

  • 4MV
  • Error resilience (data partitioning, reversible VLC decoding and slice resynchronization)
  • Short header (on demand the core can be customized to support this)

Supported image resolutions include pre-defined levels Level1 to Level5 (QCIF/CIF/VGA/SDTV) and custom definitions up to 4CIF (704x576). The core can be customized to provide support for even larger resolutions, such as HD format.

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MPEG4 Simple Profile Encoder

The MPEG-4 encoder is a hardware module optimized for FPGA technologies, making use of a limited number of logic resources and being able to encode a 4CIF (704x576) sequence in real time.  

It is fully compliant with the Video part of ISO/IEC 14496-2. All visual tools of the Simple Profile are implemented, including full support of I-VOP (intra-coded frames, without motion estimation) and P-VOP (predictive-coded frame, with motion estimation on previously encoded frame). The core is a good compromise between coding efficiency (resulting in lower bit rate for same quality), logic complexity and coding throughput, thanks to the use of an efficient motion estimation algorithm (directional search) leading to fast and precise matching, at half pixel resolution, of blocks between the current frame and its reference.  

Supported image resolutions include pre-defined levels Level1 to Level5(QCIF/CIF/VGA/SDTV) and custom definitions up to 4CIF (704x576). The core can be customized to provide support for even larger resolutions, such as HD format.  

The core features a Variable Bit Rate mode (VBR mode: fixed, user-specified quality). It can optionally also provide Constant Bit Rates (CBR mode: with regulation of the output bit rate) by using an external small microprocessor running a rate allocation algorithm (such as Nios or Microblaze). When used in CBR mode, the core delivers high-quality regulation thanks to its patented rate allocation algorithm making use of statistical information available at the motion estimation engine.

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MPEG4 ASP Decoder (D1)

This MPEG4 Decoder core is based on MPEG4 Visual (high efficiency image compression standard ISO/IEC 14496-2), and is verified to work in FPGA. Comparing with MPEG2, it is suitable for the usage at low bit rate and enales to adapt various applications such as mobile handsets, like mobile phone and PDAs, digital cameras and streaming media services through network.

Features

  • MPEG4 Visual ASP(Advanced Simple Profile) Level 1~5
  • Compliance with the AMBA Spec 2.0
  • Image size : ~ D1(720x480)
  • Support I-VOP, P-VOP and B-VOP
  • Video input format : YUV4:2:0(D1, VGA, QVGA, CIF, QCIF, SQCIF)
  • DC/AC prediction
  • 4-MV, Unrestricted MV
  • Half-pixel/quarter-pixel motion compensation
  • 8x8 block motion compensation
  • MPEG quantization
  • Error concealment : slice re-synchronization
  • Support short video header for H.263
  • low power consumption
  • high quality image (rate control, automatic scene change detection function)
  • Interface specifications easy to connect processors
  • Frame rate : 7.5 ~ 30fps
  • Gate size : 150K gate
  • Operating frequency : 60MHz (D1, 30fps)
  • SRAM size : 22K bytes
  • Verified to work in FPGA

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MPEG4 ASP Encoder (D1)

This MPEG4 Encoder core is based on MPEG4 Visual (high efficiency image compression standard ISO/IEC 14496-2), and is verified to work in FPGA. Comparing with MPEG2, it is suitable for the usage at low bit rate and enales to adapt various applications such as mobile handsets, like mobile phone and PDAs, digital cameras and streaming media services through network.

Features

  • MPEG4 Visual ASP(Advanced Simple Profile) Level 1~5
  • Compliance with the AMBA Spec 2.0
  • Image size : ~ D1(720x480)
  • Support I-VOP, P-VOP and B-VOP
  • Video input format : YUV4:2:0(D1, VGA, QVGA, CIF, QCIF, SQCIF)
  • DC/AC prediction
  • Unrestricted MV
  • Half-pixel motion compensation
  • 8x8 block motion compensation
  • MPEG quantization
  • with built-in bit rate control : single pass variable bit rate (VBR) and constant bit rate (CBR) encoding
  • low power consumption
  • high quality image (rate control, automatic scene change detection function)
  • Interface specifications easy to connect processors
  • Bit rate : 64Kbps ~ 8Mbps
  • Frame rate : 7.5 ~ 30fps
  • Gate size : 300K gate
  • Operating frequency : 60MHz (D1, 30fps)
  • SRAM size : 32K bytes
  • Verified to work in FPGA

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MPEG2 4:2:2 Profile Decoder

This core is designed to decode 4:2:2 MPEG2 elementary video streams (ISO standard 13818-2).  Two versions of the core are available, with the fast version capable of supporting the real-time decode of high level streams at clock speeds of less than 100MHz, making it suitable for implementing in an FPGA design:  

The standard core, capable of real-time decode of main level (PAL or NTSC) streams at 33MHz in an FPGA. 

A fast, parallelized core capable of supporting main level streams at 16MHz and high level streams (720p60 or 1080i60) at 100MHz in an FPGA.  

The core accepts an elementary stream and produces decoded YUV video. The host processor requirements are minimal, amounting to the memory management, and scanning the bitstream for picture start codes. Only a few registers specifying the frame locations and coding options require programming at the beginning of each picture. The core requires an external memory component, which may be shared with the host processor.  

Scaling and de-interlacing (for progressive displays) can be performed in additional post-processing hardware blocks.

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MPEG2 HD Encoder (1920x1080)

 

MPEG2 HD Decoder (1920x1080)

 

Baseline DCT-JPEG Encoder

The JPEG core is intended for high-speed encoding of gray-scale, colour or multi-scan images coded with ISO/IEC 10918-1 baseline coding standard. The encoder supports all features of the baseline standard, including restart markers, DNL, user-definable comments and application markers. It is able to encode abbreviated-format or full-format images, with pre-defined default entropy and quantization tables if preferred.

Its autonomous behaviour, its simple FIFO-like interfaces and its 100% synchronous structure allow to integrate it very easily in a complex system with few effort. This is reinforced by the stand-alone ability of the encoder that allows to instanciate it in systems with few CPU intervention.

Features

  • High-speed sustained single clock cycle per pixel component encoding
  • Single clock cycle Huffman encoding
  • 100 % baseline ISO/IEC 10918-1 JPEG compliance for colour images (single- and multi-scan formats) extending to effective 255-scan support
  • Full header building capability and automatic internal Huffman and quantization tables programming based on header data
  • Full JPEG format and abbreviated format support, including restart markers and restart interval
  • One-pass encoding scheme with bit rate regulation if enabled
  • Simple FIFO interfaces for compressed data (32 bits) and pixel interfaces (8 bits)
  • Simple CPU interface for encoder and headers programming
  • Easy-to-use status and control interface
  • Programmable external interrupt for event follow-up
  • Four entropy tables (two DC, two AC), four quantization tables
  • Burst image-sequence encoding support for images with identical tables
  • 8 bits/pixel component
  • 8x8 block-format pixel input with classical scan order (row by row from left to right)
  • Fully synchronous hardware design
  • Fully stallable compressed-data and pixel interfaces
  • Throughputs ranging from sub CIF 25Hz to SDTV to HDTV1280x720 50Hz

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High Speed Baseline DCT-JPEG Decoder

The JPEG core is intended for high-speed decoding of gray-scale, colour or multi-scan images coded with ISO/IEC 10918-1 baseline coding standard. The decoder supports all features of the baseline standard, including restart markers and full header parsing. It is able to decode abbreviated-format or full-format images, automatically extracting the quantization and entropy tables.

Its autonomous behaviour, its simple FIFO-like interfaces and its 100% synchronous structure allow to integrate it very easily in a complex system with few effort. This is reinforced by the stand-alone ability of the decoder that allows to instanciate it in systems without CPU intervention.

Features

  • High-speed sustained single clock cycle per pixel component decoding
  • Single clock cycle Huffman decoding
  • 100 % baseline ISO/IEC 10918-1 JPEG compliance for colour images (single- and multi-scan formats) extending to effective 256-scan support
  • Full header parsing capability and automatic on-the-fly Huffman and quantization tables reprogramming from header data
  • Header error catching features
  • Full JPEG format and abbreviated format support, including restart markers
  • Simple FIFO interfaces for compressed data (32 bits) and pixel interfaces (8 bits)
  • Simple CPU interface for decoder programming
  • Easy-to-use status and control interface through six internal registers
  • Programmable external interrupt for event follow-up
  • Four entropy tables (two DC, two AC), four quantization tables
  • Burst image-sequence decoding support for images with identical tables
  • 8 bits/pixel component
  • 8x8 block-format pixel output with classical scan order (row by row from left to right)
  • Fully synchronous hardware design
  • Fully stallable compressed-data interface; stallable pixel interface on a block-by-block basis
  • IEEE 1180-1990 compatible IDCT for number precision requirements
  • Throughputs ranging from sub CIF 25Hz to SDTV to HDTV1280x720 50Hz

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High Speed Baseline DCT-JPEG Codec

Features

  • Half duplex JPEG codec  
  • High-speed sustained single clock cycle per pixel component encoding and decoding  
  • Single clock cycle Huffman decoding and encoding  
  • 100% baseline ISO/IEC 10918-1 JPEG compliance for color images (single and multi-scan formats) extending to effective 255-scan support.  
  • Full header generation capability with default pre-programmed Huffman and quantization tables or user-definable custom tables in encoding mode.  
  • Full header parsing capability and automatic on-the-fly Huffman and quantization tables reprogramming from header data in decoding mode,  
  • One-pass encoding scheme with compression ratio regulation.  
  • Header error catching features  
  • Full baseline JPEG format and abbreviated format support, including restart markers and DNL.  
  • Simple FIFO interfaces for compressed data (32 bit) and pixel interface (8 bit)  
  • Simple CPU interface for codec control and programming.  
  • Easy-to-use status and control interface through 21 internal registers.  
  • Programmable external interrupts for event follow-up.  
  • For entropy tables (two DC, two AC), four quantization tables.  
  • Burst image-sequence encoding support for images with identical tables and color format.  
  • Burst image-sequence decoding support for images with identical tables.  
  • 8-bit/pixel components.  
  • 8x8 block format pixel interface with classical scan order (row by row from left to right).  
  • Fully synchronous hardware design.  
  • Fully stallable compressed dat-interface, stallable pixel interface on a block-by-block basis.  
  • Throughputs ranging from sub CIF 25Hz to SDTV to HDTV1280x720 50Hz

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DCI JPEG2000 Decoder

Capitalizing on its long-term experience with JPEG2000 hardware coding, the company has extended its JPEG2000 portfolio by releasing a new smaller real-time hardware decoder engine that is optimized for Digital Cinema. The core architecture offers a flexible and high-speed solution to the performance challenges of the DCI recommendation. It is able to sustain the high decoding requirements of the large DCI frame formats, including 4096x2160 resolution and frame rates up to 48 frames per second.

The JPEG2000D IP core is a JPEG2000 hardware decoder dedicated to DCI application (Digital Cinema Initiatives). It decodes streams compliant with the ISO/IEC 15444-1 specification (JPEG2000) that follow the DCI recommendation for video coding. It applies JPEG2000 decoding on un-tiled large color frames with 4:4:4 color resolution.

The core performs the complete video decompression operations of the normalized decoding process: the stream parsing and header decoding, the entropy decoding, inverse quantization, inverse discrete wavelet transform (IDWT) and inverse color transform (ICT). It expects a JPEG2000 DCI compliant stream at its input interface and generates decoded 12-bit XYZ samples at its output interface.

The core is optimized for speed and is able to deal with the demanding DCI processing speed: it is able to provide a single-chip FPGA solution for both 2K @24 fps and 2K @48fps distributions. Moreover it is 4K ready and can perform real-time 4K @24fps decoding. The flexible FPGA architecture allows the user to build a secure decoder by integrating Barco Silex cryptography decoders (AES).

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DCI JPEG2000 Encoder

Capitalizing on its long-term experience with JPEG2000 hardware coding, the company has extended its JPEG2000 portfolio by releasing a real-time hardware encoder engine that is optimized for Digital Cinema. The core architecture offers a flexible and high-speed solution to the performance challenges of the DCI recommendation. It is able to sustain the high encoding requirements of the large DCI frame formats, including 4096x2160 resolution and frame rates up to 48 frames per second.  

The JPEG2000E IP core is a JPEG2000 hardware encoder dedicated to DCI application (Digital Cinema Initiatives). It applies JPEG2000 encoding on un-tiled large color frames with 4:4:4 color resolution. Coupled with the optional rate allocator (Tier-2) it generates streams compliant with the ISO/IEC 15444-1 specification (JPEG2000) and following the DCI recommendation for video coding.  

The core performs the following video compression operations of the normalized encoding process: discrete wavelet transform (DWT), quantization and entropy encoding. It expects 3x12-bit samples at its input interface and generates a JPEG2000 DCI codestream at its output interface. This codestream can then be embedded in a standard JPEG2000 file format.  

The core is optimized for speed and is able to deal with the demanding DCI processing speed: it is able to provide a single-chip FPGA solution for all 2K @24 fps, 2K @48fps and 4K @24fps distributions. A single core encodes a 2K DCI stream at 24fps. The core is 4K ready and can encode 4K frames. The flexible FPGA architecture allows the user to build a secure encoder by integrating Barco Silex cryptography encoders (DCI AES).

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JPEG2000 Encoder

The core is a JPEG2000 hardware accelerator dedicated to image compression applications in either lossy or lossless environment with full support of the ISO/IEC 15444-1 specification (JPEG2000).  

The core performs the computing-intensive operations of the normalized encoding process (also called Tier-1): the Discrete Wavelet transform, quantization and entropy encoding. The last part of the JPEG2000 encoding process, known as Tier-2 encoding (i.e. bit rate allocation and packet reordering), is more suitably achieved in software by the host processor.  

For achieving high compression throughputs the IP core can be configured at synthesis stage in order to implement several entropy channels in parallel. This makes the core suitable for compression applications with target speeds compatible with real-time video (e.g SDTV or higher).

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JPEG2000 Decoder

The core is a JPEG2000 hardware accelerator dedicated to image compression applications in either lossy or lossless environment with full support of the ISO/IEC 15444-1 specification (JPEG2000).  

The core performs the computing-intensive operations of the normalized decoding process (also called Tier-1): the entropy decoding, inverse quantization and inverse Discrete Wavelet transform. The first part of the JPEG2000 decoding process, known as Tier-2 decoding (i.e. packet reordering), is more suitably achieved in software by the host processor.  

For achieving high decompression throughputs the IP core can be configured at synthesis stage in order to implement several entropy channels in parallel. This makes the core suitable for decompression applications with target speeds compatible with real-time video (e.g SDTV or higher).

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Motion JPEG (MJPEG) encoder and decoder

Motion JPEG (MJPEG) encoder and decoder IP cores support real-time encoding and decoding of JPEG compliant still images at up to 30 fps video rates. This small flexible implementation is ideal for still image, video transmission and storage applications. Available in VHDL , the "IP" core is designed for rapid integration into your FPGA or ASIC-based system.

Features

  • VHDL design, suitable for synthesis to FPGA or ASIC.
  • Encoder occupies approximately 60% of the low cost Xilinx Spartan 2e 300K device and will encode CIF resolution at over 30 fps.
  • Adds compliant JPEG headers without external processor intervention.
  • Can be supplied on FPGA evaluation board for the PC with evaluation software.

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Digital NTSC/PAL Video Encoder

Features

  •     RGB, ITU-R 601/656 YCbCr to NTSC/ PAL Video Encoder
  •     10-bit Digital Output for High Quality external 10-bit Video DACs
  •     NTSC-M/J/4.43, PAL-B/D/G/H/I/M/N/combination N
  •     Single 27 MHz Clock Required (x2 Oversampling)
  •     32-bit Direct Digital Synthesizer for Color Subcarrier
  •     Video Output Support:
    • Composite (CVBS)
    • Component S-Video (Y/C)
  •     Video Input Data Port Supports:
    • RGB 24-bit Parallel Input Format
    • ITU-R BT.601 4:2:2 16-bit Parallel Input Format
    • ITU-R BT.656 8-bit Parallel Input Format
  •     Programmable Luma Filters
  •     Programmable Chroma Filters
  •     Programmable Subcarrier Phase
  •     Programmable Luma Delay
  •     Programmable Chroma Delay
  •     Control Signals for Individual On/Off switch of Each external DAC
  •     Onboard Pattern Generation (Color bar, Ramp, Stair, Hatch)

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Bilinear Image Scaler

 

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