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[Home][IP][Microprocessor]

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8051 Pipelined  Microcontroller

The CPU is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management unit PMU.

The CPU soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. There are two configurations of CPU: Harward where internal data and program buses are separated, and von Neumann with common program and external data bus. The CPU has Pipelined RISC architecture 10 times faster compared to standard architecture and executes 85-200 million instructions per second. This performance can also be exploited to great advantage in low power applications where the core can be clocked over ten times more slower than the original implementation, without performance depletion.

The CPU is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.

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PIC 8-bit RISC Microcontroller

The CPU is a low-cost, high performance, 8-bit, fully static soft IP Core, dedicated for operation with fast memory (typically on-chip). The core has been designed with a special concern about low power consumption.

The CPU is software compatible with the industry standard PIC16C54, PIC16C55, PIC16C56, PIC16C57 and PIC16C58. It employs a modified RISC architecture (2 times faster than original implementation).

The CPU have enhanced core features and configurable hardware stack. The separate instruction and data buses allow a 12 bit wide instruction word with the separate 8-bit wide data. The CPU typically achieve a 2:1 code compression and a 8:1 speed improvement over other 8-bit microcontrollers in its class. The Core has 24 I/O lines and an 8-bit timer/counter with an 8-bit programmable prescaller.

The power-down mode SLEEP allow user to reduce power consumption. User can wake up the controller from SLEEP through an user reset or watchdog overflow. An integrated Watchdog Timer with it's own clock signal provides protection against software lock-up.

The Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode and small used area in programmable devices make this IP perfect for applications applications with space and power consumption limitations.

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Configurable 8-bit RISC Microcontroller

The CPU is a low-cost, high performance, 8-bit, fully static soft IP Core, dedicated for operation with fast dual ported memory. The core has been designed with a special concern about low power consumption assuring the best power consumption, price and performance combination on the IP market.

The CPU soft core is software compatible with the industry standard PIC 16XXX Microcontrollers.... It implements an enhanced Harvard architecture (separate instruction and data memories) with independent address and data buses. The 14 bit program memory and 8-bit dual port data memory allow instruction fetch and data operations to occur simultaneously. The advantage of this architecture is that instruction fetch and memory transfers can be overlapped by multi stage pipeline, so that the next instruction can be fetched from program memory while the current instruction is executed with data from the data memory. The CPU architecture is 4 times faster compared to standard architecture. So most instructions are executed within 1 system clock period, except the instructions which directly operates on program counter PC (GOTO, CALL, RETURN), this situation require the pipeline to be cleared and subsequently refilled. This operation takes additional one clock cycle.

The Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode make this IP perfect for applications where power consumption is critical.

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Z80 compatible 8-bit Microprocessor

The DZ80 is an advanced 8-bit microprocessor with 208 bits of user accessible registers, composed of six general purpose registers, able to be used individually as either 8-bit registers, or as 16-bit register pairs. Additionally to those registers, DZ80 supports two sets of accumulator and flag registers. The DZ80 contains also Stack Pointer, program Counter, two index registers, a REFRESH register, and an INTERRUPT register. All output signals are fully decoded and timed to control standard memory or peripheral circuits.

The DZ80 is supported by a wide range of peripherals family.

DZ80 is fully customizable, which means it is delivered in the exact configuration to meet users requirements. There is no need to pay extra for not used features and wasted silicon.

It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.

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80390 Pipelined Microcontroller

The CPU is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. It supports up to 8 MB of linear code space and 16 MB of linear data space. This ratio is extended by an advanced power management unit PMU.

The CPU soft core is 100% binary-compatible with the industry standard 80390 & 8051 8-bit microcontroller. There are two configurations of the CPU: Harward where internal data and program buses are separated, and von Neumann with common program and external data bus. The CPU has Pipelined RISC architecture 10 times faster compared to standard architecture and executes 85-200 million instructions per second. This performance can also be exploited to great advantage in low power applications where the core can be clocked over ten times more slower than the original implementation, without performance depletion.

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68HC111 8-bit FAST Microcontroller

This is a advanced 8-bit MCU IP Core. This CPU soft core is binary-compatible with the industry standard 68HC11 8-bit microcontroller and can achieve a performance 45-100 million instructions per second. There are two configurations of  this CPU:

  • Harvard - where data and program buses are separated,
  • Von Neumann - with common program and data bus.

This CPU has FAST architecture that is 4.4 times faster compared to original implementation.

Self-monitoring circuitry is included on-chip to protect against system errors. An illegal opcode detection circuit provides a non-maskable interrupt if illegal opcode is detected.

Two software-controlled power-saving modes, WAIT and STOP, are available to conserve additional power. These modes make this CPU IP Core especially attractive for automotive and battery-driven applications.

This CPU have built in the development support features designed into the CPU. The LIR signal is intended as a debugging aid. This signal is driven to active low for the first bus cycle of each new instruction, making it easy to reverse assemble (disassemble) instructions from the display of a logic analyzer.

This CPU is fully customizable, which means it is delivered in the exact configuration to meet users¡¯ requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.

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16/32-bit CISC 68000 Microprocessor

D68000 soft core is binary-compatible with the industry standard 68000 32-bit microcoprocessor. D68000 has a 16-bit data bus and 24-bit ad-dress data bus. It is code compatible with the MC68008 and is upward code compatible with the MC68010 virtual extensions and the MC68020 32-bit implementation of the architecture. D68000 has improved instructions set allows execution of a program with higher per-formance than standard 68000 core.

D68000 is delivered with fully automated test-bench and complete set of tests allowing easy package validation at each stage of SoC design flow. A special testing paltfrom has been built to run D68000 with uCLinux Operating System.

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32-bit Configurable RISC/DSP core

This Processor Core is a 32-bit embedded processor in the same class as ARM9 processors. It can be configured with L1 insn/data caches and MMUs to run Linux or configured to work without L1 caches or MMUs for running real-time operating systems and firmware. 

Features

  • High Performance 32-Bit CPU/DSP
  • L1 Caches
  • QMEM and Store Buffer
  • Memory Management Unit
  • Power Management Unit
  • Advanced Debug Unit
  • Integrated Tick Timer
  • Programmable Interrupt Controller
  • Custom and Optional Units
  • System Interface

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