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[Ż├└█][IP][Connectivity]

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USB
 

Secure Digital (SD & SDIO) Solutions

PCI/Cardbus

 

CF Controller

Smart Card Interface Controller

 

ATA Host Controller

 

USB 1.1 Device

The USB 1.1 Device IP Core is an USB 1.1 compliant device core with optional AHB, APB, PCI, or Custom bus interface. The USB 1.1 device core supports 12 Mbit/s in Full Speed (FS) mode and 1.5 Mbit/s in Low Speed (LS) mode.

The USB 1.1 Device IP Core is highly configurable. The control endpoints and Serial Interface Engine (SIE) comprise of the basic building block of an USB 1.1 application. A design can be customized by adding the required number of bulk, interrupt, control, and isochronous endpoints. The control endpoint responsible for the configuration of the USB device, controlling of certain aspects of the deviceí»s operation, issuing of commands, reading of descriptors, and assignment of unique address to a device. A ROM can be included to hold the operational and control data for the control endpoints. Each isochronous endpoint comes with a ping-pong buffer suitable for isochronous data transfers.

The USB 1.1 Device IP Core is an RTL design in Verilog that implements an USB device controller on an ASIC or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications. The IP core is silicon proven and in production with multiple customers.

Features

  • USB 1.1 compliant
  • Supports 12 Mbit/s (FS) and 1.5 Mbit/s (LS) transfer rate
  • Supports all USB standard requests
  • Supports class specific commands
  • Ping-pong buffer for each isochronous endpoint
  • Optional ROM for control endpoint configurations
  • Expandable number of bulk, interrupt, control, and isochronous endpoints
  • Digital phase lock loop recovery scheme
  • Optional 300 MHz 32-bit AHB or APB bus
  • Optional 33 MHz PCI Rev. 2.2 bus
  • Optional Custom bus for x86, SH3, 8051, ARM, ARC, and other processors
  • Technology independent design
  • Comprehensive test bench available

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USB 1.1 Host

The USB 1.1 Host IP Core is an USB 1.1 compliant host core with an optional AHB, APB, PCI, or Custom bus interface. The USB 1.1 host core supports 12 Mbit/s in Full Speed (FS) mode and 1.5 Mbit/s in Low Speed (LS) mode.

The support on AHB, APB, PCI and Custom buses provides a direct interface to a wide variety of processors such as the ARM, x86, 8051, SH3, and ARC.The USB 1.1 Host IP Core implements the USB 1.1 host controller that compliant to the OHCI 1.0 specification.The USB host controller consists of the CPU host interface, OHCI List Processor, Host Serial Interface Engine, and USB 1.1 Root Hub. The Root Hub supports three downstream ports and is expandable as required. Up to a maximum of 127 devices can be supported by the USB host controller. The USB 1.1 Device IP Core consists of a 32-bytes PCI FIFO, and two 32-bytes ping-pong buffers for handling USB IN/OUT transfers.

The USB 1.1 Device IP Core is an RTL design in that implements an USB device controller on an ASIC or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications. The IP core is silicon proven and in production with multiple customers.

Features

  • USB 1.1 compliant
  • Supports 12 Mbit/s (FS) and 1.5 Mbit/s (LS) transfer rates
  • Supports 127 devices
  • Three downstream USB 1.1 ports
  • Compliant to Open Host Controller Interface (OHCI)
  • Supports asynchronous communication between CPU host and USB devices
  • 48 MHz system clock
  • 32-bytes PCI FIFO
  • Two 32-byte ping-pong buffers for USB IN/OUT transfers
  • Synthesizable VHDL/Verilog source code
  • Optional 300 MHz 32-bit AHB or APB bus
  • Optional 33 MHz PCI Rev. 2.2 bus
  • Optional Custom bus for x86, SH3, 8051, ARM, ARC, and other processors
  • Technology independent design
  • Comprehensive test bench available

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USB 1.1 Hub

The USB 1.1 Hub IP Core is an USB 1.1 compliant hub core. The hub IP core supports 12 Mbit/s in Full Speed (FS) mode and 1.5 Mbit/s in Low Speed (LS) mode. The USB 1.1 Hub IP Core consists of Hub Controller and Repeater. The Hub Controller provides the mechanism for host to hub communication. Hub class specific commands, as well as USB standard commands are interpreted by the Host Controller to configure, monitor, and control the hub and its downstream ports.The hub repeater handles the connectivity between the upstream and downstream ports. The USB 1.1 Hub IP Core supports multiple number of downstream ports that meet the requirements of an application. The Hub IP Core interfaces directly with standard USB transceivers such as the Philips ISP 1501BE. Software utilities is available that enhances the performance of the USB 1.1 Hub IP Core. The Autogen utility can be used for generation of descriptors, and the easy-to-use Auto-configure utility can be used for wiring of downstream ports.

The USB 1.1 Hub IP Core is an RTL design in Verilog that implements an USB hub controller on an ASIC or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications.

Features

  • USB 1.1 compliant
  • Supports 12 Mbit/s (FS) and 1.5 Mbit/s (LS) transfer rates
  • Supports all hub specific commands
  • Supports multiple downstream ports
  • Easy-to-use Auto-configure utility for wiring of downstream ports
  • Autogen utility for generation of descriptors
  • supports suspend/resume for power management
  • Downstream device connect/disconnect detection
  • Provision of port indicators for downstream ports
  • Synthesizable VHDL/Verilog source code
  • Technology independent design
  • Comprehensive test bench available

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USB 2.0 Device

The USB 2.0 Device IP Core is an USB 2.0 compliant device core with optional PCI, Custom, or AHB master/slave interfaces. The USB 2.0 device core supports 480 Mbit/s in High Speed (HS) mode. 12 Mbit/s in Full Speed (FS) mode, and 1.5 Mbit/s in Low Speed (LS) mode. The USB 2.0 Device IP Core supports up to 30 configurable IN/OUT non-control endpoints. Each noncontrol endpoint has an endpoint controller that supports interrupt, bulk, and isochronous transfers. There is one control endpoint that handles the setup, data, and status stages during control transfers. Auto Validation, Manual Validation, or Fly mode can be selected to reduce loading of the host CPU during in-transfer operations. The USB 2.0 Device IP Core includes a DMA controller for handling high-speed data transfers between the USB 2.0 device core and PCI/Custom/AHB interface. With the addition of an ULPI Wrapper, the USB 2.0 Device IP Core can be connected directly to a standard UTMI or 8-bit ULPI transceiver.

The USB 2.0 Device IP Core is an RTL design in Verilog that implements an USB device controller on an ASIC or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications.

Features

  • USB Specification Rev. 2.0 compliant
  • Supports 16-bit UTMI and 8-bit ULPI interfaces
  • Direct addressing of all registers from PCI, Custom, or AHB bus
  • Software control of device remote wake-up
  • DMA controller supports highspeed data transfers between USB device and PCI/Custom/AHB host
  • Supports a maximum of 15 configurable IN and 15 configurable OUT endpoints
  • Each IN or OUT endpoint supports Isochronous, Bulk, and Interrupt transfers
  • Auto Validation, Manual Validation, and Fly modes support for in-transfer of data to the host
  • Dual-port RAMs as end point buffers
  • Supports maximum 1024 bytes packet size for each endpoint
  • Supports 8, 16, 32-bit PCI/Custom/ AHB bus

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USB 2.0 Host

The USB 2.0 Host IP Core is an USB 2.0 specification compliant host core with optional PCI, Custom, or AHB master/slave interfaces. The USB 2.0 host core supports 480 Mbit/s in High Speed (HS) mode. 12 Mbit/s in Full Speed (FS) mode, and 1.5 Mbit/s in Low Speed (LS) mode.

The USB 2.0 Host IP Core consists of an Enhanced Host Controller Interface (EHCI) and a companion Open Host Controller Interface (OHCI). The EHCI processor handles HS transactions and is the default owner of the Root Hub that connects to downstream ports. In a downstream data transfer, the EHCI sends data to the Host Parallel Interface Engine (HPIE) for encoding and CRC appending. Data received by the USB 2.0 Root Hub is forwarded to downstream ports through the Root Hub. Similarly, FS and LS transactions are handled by the OHCI, Host Serial Interface Engine (HSIE), and USB 1.1 Root Hub. The Root Hub performs multiplexing and forwarding of packets between the downstream ports and USB 2.0/1.1 Root Hubs. Up to 8 downstream ports can be connected to the USB 2.0 Host IP Core. With the addition of optional ULPI Wrappers, the USB 2.0 Host IP Core can be connected directly to standard UTMI or 8-bit ULPI transceivers. The USB 2.0 Host IP Core is an RTL design in Verilog and VHDL that implements an USB host controller on an ASIC or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications.

Features

  • USB Specification Rev. 2.0 compliant
  • Supports up to 127 devices and 8 downstream ports
  • Compliant with EHCI Rev. 1.0 specification
  • OHCI companion processor for UBS 1.1 transfers
  • Supports 16-bit UTMI and 8-bit ULPI interfaces
  • Direct addressing of all IP Core registers from PCI, Custom, or AHB bus
  • DMA controller supports highspeed data transfers between USB Host and PCI/Custom/AHB host
  • Supports 8, 16, 32-bit PCI/Custom/AHB bus
  • Optional 33 MHz PCI Rev. 2.2 master/target interface
  • Optional 133 MHz AHB Rev. 2.0 master/slave interface
  • Optional Custom bus interface

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USB 2.0 Hub

The USB 2.0 Hub IP Core is an USB 2.0 specification compliant hub core that supports 480 Mbit/s in High Speed (HS) mode, 12 Mbit/s in Full Speed (FS) mode, and 1.5 Mbit/s in Low Speed (LS) mode.

The USB 2.0 Hub IP Core consists of the Hub Controller, Hub Repeater, Transaction Translators, Routing Logic, and Downstream Ports. The Hub Controller controls the operation of the USB hub by interpreting both the USB commands and Hub class specific commands. High-speed packets originated from the root hub are forwarded by the Hub Repeater to the HS Downstream Ports through the Routing Logic. Full-speed and low-speed packets scheduled by the host system software as split transactions are forwarded to the Transaction Translator. The Transaction Translator handles split transactions that convey isochronous, interrupt, control, and bulk transfers across the high-speed bus to and from full-speed and low-speed devices that attached to the hub. The Transaction Translator also performs CRC on incoming packets from Hub Repeater or Routing Logic. The Routing Logic connects the Hub Repeater to the Downstream Ports in highspeed transfers, and it connects the Transaction Translator to the Downstream Ports in full-speed and low-speed transfers. The number of Downstream Ports is scalable.

The Auto-configure and Auto-wire are pre-compiled C language utilities that allow users to have the freedom to fully customize their designs.

Features

  • USB Specification Rev. 2.0 compliant
  • Expandable number of downstream ports
  • Supports all hub specific requests
  • Easy to use Auto-configuration utility for wiring downstream ports
  • Autogen utility for descriptors generation
  • Dedicated Transaction Translator for each downstream port
  • Connect/disconnect detection of downstream ports
  • Supports suspend/resume for power management
  • Provision of port indicators for downstream ports
  • UTMI Rev. 1.05 compatible downstream and upstream transceiver interface
  • Optional ULPI transceiver interface

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USB OTG Core

The USB 2.0 OTG IP Core is compliant with the OTG Supplement Rev. 1.0a. The USB 2.0 OTG core supports both Host Controller, Device Controller and OTG functionality. When operating as a host (or A-device), it supports 480 Mbit/s in High Speed (HS) mode, 12 Mbit/s in Full Speed (FS) mode, and 1.5 Mbit/s in Low Speed (LS) mode. When operating as a peripheral (or B-device), it supports HS and FS modes. Optional AHB, PCI, and Custom buses are available to provide high-speed connection to the USB interface.

Session Request Protocol (SRP) and Host Negotiation Protocol (HNP) are managed by the SRP/HNP Control Logic. SRP allows a B-device to request an A-device to turn on Vbus to start a session, while HNP allows two connected dual-role devices to change roles and eliminates the needs for the user to switch cable connections. The Vbus Control Circuit supports the generation of data-line pulsing and Vbus pulsing methods when initiating the SRP as a B-device, the detection of both pulsing methods when acting as an A-device, and the sourcing of a minimum of 8 mA on Vbus. The Vbus Control Circuit also handles the pull-up and pull-down connections to D+ and D- during host/device role switching. The SRP/HNP Logic and Vbus Control Circuit control the operating mode of an USB port as either a host or peripheral. Up to 5 USB OTG ports can be supported by the Arasan USB 2.0 OTG IP Core. Each USB 2.0 OTG port requires an external USB 2.0 transceivers with standard UTMI interfaces.

The USB 2.0 OTG IP Core offers a high level of flexibility by allowing designers to implement multiple USB 2.0 OTG ports with a wide selection of processor interfaces. The USB 2.0 OTG IP Core is augmented by the availability of the Arasan OTG Software Stack that supports host driver, device driver, class of devices, and Linux operating system. The USB 2.0 OTG IP Core is an RTL design in Verilog and VHDL that implements an USB 2.0 OTG controller on an ASIC or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications.

Features

  • Compliant with OTG Supplement Rev. 1.0a
  • Supports 480 Mbit/s (HS), 12 Mbit/s (FS), and 1.5 Mbit/s (LS) as a host or A-device
  • Supports 12 Mbit/s (FS), and 1.5 Mbit/s (LS) as a peripheral or Bdevice
  • Supports Session Request Protocol (SRP) and Host Negotiation Protocol (HNP)
  • Up to 5 USB OTG ports can be implemented
  • Supports data-line pulsing and Vbus pulsing as A-device or Bdevice
  • USB transaction protocols are handled by hardware
  • Standard UTMI USB 2.0 transceiver interface
  • Minimum 8 mA Vbus and over 500 ma sourcing to peripherals with 5 V external power supply
  • Direct addressing of all IP core registers from PCI, AHB, or Custom bus
  • Suspend/resume support for power management
  • Optional 300 MHz 32-bit AHB bus
  • Optional 33 MHz PCI Rev. 2.2 bus
  • Optional Custom bus for x86, SH3, 8051, ARM, ARC, and other processors

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SDIO/SD Memory/MMC Host Controller

The Core is a host controller for SD memory card, SDIO and MMC interface. The core connects the host CPU of the system to the SD card socket. External SD cards can be accessed by the host CPU through the controller core IP.

SD memory and SDIO are low cost, high speed interfaces designed for removable mass storage and IO devices. It is a very flexible architecture supporting variable clock rate and 1 to 4-bit SD data width. Data rate of up to 25Mbyte/sec (200Mbs) can be realized with SD interface. Features such as plug and play, auto-detection, error correction, write protection are standard with SD card interface.

The SD card host controller core is designed according to the SD Associationí»s SD host controller specification. The core presents a very simple view of the SD card to the system software. All access to the SD card are made through the standard control register set. DMA, burst access, CRC error detection, interrupt, timing, etc. are supported by the controller core. Because of the standard register set, the Core can be used to replace other existing SD controllers with no change to system software.

There are several options for user hardware interface to the controller core. The controller supports generic user interface optimized for on-chip logic interface as well as embedded CPU interface such as AMBA AHB bus. To access the SD card, the host CPU simply issue read/write access to the control registers in the core. The controllers core handles all the SD card protocol automatically including data shifting, timing and CRC generation. The core has a built-in DMA controller so that data can be automatically transferred between the system and the SD card without CPU intervention.

With the Core, SD card interface can be realized with very little development cost. Designer can add SD memory and SDIO interface to the system by simply adding the Core module without changing the rest of the system architecture.

Features

  • Host controller for SDIO, SD memory card, and MMC interface.
  • Allows host CPU to access SD and MMC devices.
  • Simple user interface optimized for on-chip bus connection.
  • User interface supports 32-bit and 64-bit data.
  • Option to integrate with other CPU bus slaves to support direct access by various CPUí»s including PowerPC, MPC860, ARM, SH2/3/4, MIPS, and ARC microprocessors.
  • Supports SDIO DMA operation for high speed data transfer.
  • Supports SD host controller standard register set.
  • Fully programmable access timing.
  • Hardware support of CRC error detection and interrupt generation
  • Supports multi-function SD cards, command suspend, resume, and block transfers.
  • Option to operate the user interface and card interface at different clock domains.
  • Direct mapping of host address space to card address space.
  • Designed for ASIC and FPGA implementations.
  • Fully static design with edge triggered flip-flops.
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    SDIO/SD Memory/MMC Slave Controller

    The Core is a slave controller for SD memory card, SDIO and MMC interface.

    Features

  • Slave controller for SDIO, SD memory card, and MMC interface.
  • Compatible with SD specification 2.0 and SDIO 1.2
  • Provides SD interface to peripheral or memory device through a simple address/data interface
  • Support SD and SPI bus protocol
  • Option to integrate with other standard CPU buses such as AMBA AHB, PowerPC, MIPS, etc.
  • Maximum transfer rate of 25Mbyte/sec at SD interface.
  • Simple 32-bit user interface.
  • Write buffer can post up to 4086 bytes for high performance block transfer.
  • Supports maximum block size up to 2048 bytes.
  • Process most SD/SDIO commands automatically without user interference.
  • Contains SD memory/SDRIO standard slave register set.
  • Hardware CRC generation and detection.
  • Supports multi-function SD cards, command suspend, resume, block transfers and SDIO interrupts.
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    PCI/MiniPCI/CardBus

    The PCI/Mini PCI/CardBus - AHB IP Core is a 33/66 MHz highperformance PCI - AHB bridge, Mini PCI - AHB bridge, or CardBus - AHB bridge. The IP is compliant to PCI 2.2 and CardBus specifications. Applications of this IP core include Ethernet, wireless, USB, FireWire CardBus adapters, PCI add-on cards, PCMCIA adapter cards, and PCI - AHB bridges.

    The PCI Local Bus is a high performance 32-bit bus with multiplexed address and data lines. The CardBus are PCMCIA 2.1 or later standards is also a 32-bit version of the PC Card. CardBus combines the lowpower, small form-factor, hot insertion capability, and light weight of the PC Cards with the high-performance of the PCI. CardBus PC Cards support a maximum throughput of 132MB/second when operating with a Dword data bus. The CardBus cards, when inserted into a 68-pin CardBus socket, are automatically detected and configured by PCMCIA-specific software. The PCI/CardBus controller provides synchronous interface to the user applications. It acts both as a master and slave for corresponding AHB write and read transactions.

    The AMBA AHB bus addresses the requirements of high-performance synthesizable design. It also supports multiple bus masters and provides high-bandwidth operation. The AHB bus supports burst transfer, split transactions, single-cycle bus master handover, single-clock edge operation, non-tristate implementation, and wider data bus configuration (64/128 bits).

    Features

    • PCI 2.2-compliant, 32-bit, 33/66 MHz interface
    • Mini PCI Specification revision 1.0 compliant
    • CardBus compliant, 32-bit, 33MHz interface
    • Conforms to AMBA AHB specification revision 2.0
    • Compliant with PCI Bus Power Management Interface Specification revision 1.1
    • Customizable, programmable, single-chip solution
    • Predefined implementation for predictable timing
    • Supports power management event
    • Supported master functions:
      • memory read, memory write
      • interrupt acknowledge
      • parity generation / error detection
    • Supported target functions:
      • zero wait state data transfer
      • type 0 configuration space header
      • medium decode speed
      • parity generation / error detection
      • configuration read, configuration write
      • memory read, memory write
      • target abort, target retry, target disconnect

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    CF/CF+ Device Controller

    CompactFlash is used in a wide variety of applications ranging from data storage cards, magnetic disk drives, fax modem cards, and wireless pager cards. The CF cards support only common memory data storage whereas the CF+ cards expand to include I/O devices such as Ethernet cards. CompactFlash adopts the PC card (or PCMCIA 2.0) specification and therefore compatible with the PCMCIA or PC card. A 50-pin CompactFlash device can be inserted into a 68-pin PCMCIA or PC card slot with an adapter. The CompactFlash Device Controller IP core supports the CF and CF+ functionalities with a selection of host interfaces including AHB, APB, PCI, 8051, and custom buses.

    The CompactFlash Device Controller IP core has three basic modes of operation: (1) PC card ATA using I/O mode, (2) PC card ATA using memory mode, (3) PC card ATA using memory and true IDE modes. The 16-bit CF+ device controller implements the Card Information Structure (CIS), Attribute Memory control, and Status registers that handle data transfers to/from the host interface. The Function I/O registers hold device function specific information that supports communication between the CF+ host and CF+ based I/O applications. The bridge controller also implements a flexible scatter-gather DMA for data transfer between the internal FIFOs and application memory with the host master capability. The CF+ device controller is also capable of interfacing up to four endpoints in an application.

    The CF+ Device Controller IP has a host interface on the application side. The host interface supports both master and slave operations. The slave interface is used by external processor to program the I/O registers for configuring the CF+ device controller, and for programing the control of data transfer between the device controller and applicationí»s memory. The master interface is used to transfer packets between the internal FIFOs and application memory.

    Features

    • Meets CF+ or CompactFlash specification revision 2.0
    • Supports PC card ATA using memory mode
    • Supports PC card ATA using I/O mode
    • Supports PC card ATA using memory and true IDE modes
    • Supports PCMCIA version 2.0
    • Programmable through standard host interface
    • Scatter-gather DMA mode
    • Interface up to four endpoints for data transfers
    • Optional AHB / APB host interface
    • Optional PCI host interface
    • Optional 8051 interface
    • Optional custom host interface

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    CF/CF+ Host Controller

    CompactFlash is used in a wide variety of applications ranging from data storage cards, magnetic disk drives, fax modem cards, and wireless pager cards. The CF cards support only common memory data storage whereas the CF+ cards expand to include I/O devices such as the Ethernet cards. CompactFlash adopts the PC card (or PCMCIA 2.0) specification and therefore compatible with the PCMCIA or PC card. A 50-pin CompactFlash device can be inserted into a 68-pin PCMCIA or PC card slot with an adapter. The CompactFlash Controller IP core supports the CF and CF+ functionalities with a selection of host processor interfaces including AHB, APB, PCI, 8051, and custom buses.

    The CompactFlash Host Controller IP core has three basic modes of operation: (1) PC card ATA using I/O mode, (2) PC card ATA using memory mode, (3) PC card ATA using memory and true IDE modes. The CF+ host implements the Card Information Structure (CIS), Attribute Memory control, and Status registers that handle data transfers to/from the host interface. The host controller implements a flexible scatter-gather DMA for data transfer between the internal FIFOs and application memory. Up to four endpoints in an application can be supported. The CF+ host controller also allows the operation of independent CF+ clock and host processor clock. The independent clock capability provides flexibility in design as well as optimization of system performance. An optional master host processor interface can also be added to enhance data transfer rate with the DMA.

    The CF+ controller core has an 8-bit or 16-bit CF+ interface on the host side and an target/slave interface on the application side. The target/slave interface is used by external processor to program the I/O registers for CF+ host controller configuration. The target/slave interface is also used for transferring packets between the internal FIFOs and the application memory.

    Features

    • . Compliant with CompactFlash (CF+) 3.0, PC Card Standard 8.0, and PCMCIA 2.1/JIEDA 4.2
    • . Supports PC Card Memory Mode and PC Card IO Mode
    • . Supports attribute memory, common memory and IO access in PC Card/PCMCIA Mode
    • . 8-bit or 16-bit wide CF+ interface data path
    • . Scatter-gather DMA mode support at CF+ interface
    • . 25 to 100 MHz CF+ interface clock
    • . Supports advanced timing mode for IO Access
    • . Two 32 bits x 8 FIFOs between CF+ and processor interfaces
    • . Supports block data transfer with block size up to 512 bytes
    • . Interrupt driven data transfers
    • . Separate CF+ clock and processor clock to enhance performance
    • . Optional host processor master interface
    • . Optional AHB/APB host interface
    • . Optional PCI host interface
    • . Optional 8051 interface
    • . Optional custom host interface

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    PCMCIA/CompactFlash Host Adapter

    The Compactflash/PCMCIA host adapter supports all four access types as defined in the PC Card/PCMCIA/CompactFlash standards, including memory and IO access for ISA bus, common memory, attribute memory and IO access for PC Card/PCMCIA. The host adapter allows host CPU to access the PC Card/PCMCIA and CompactFlash cards. Different options of user interfaces are available. In the most basic form, the core contains a simple user interface which is optimized for on-chip connections. The user interface is modeled after generic microprocessor interface. 

    This Compactflash controller core can also be integrated with other CPU bus slaves to interface directly with other embedded CPUs. The CPU supported are ARM (with AMBA AHB bus), PowerPC (with 60X bus or MPC860 bus), MIPS (with SysAD bus or EC interface), ARC and Hitachi SH2, SH3 and SH4 embedded processors. 

    The host adapter supports different types common memory access, attribute memory access and IO access for PC Card/PCMCIA/CompactFlash. It also supports True IDE mode in CompactFlash. Different chip select signal is provided for the CPU or user logic to select the address space being accessed.  

    The basic CPU interface can be 32 or 64-bit while the card interface can be either 8-bit or 16-bit. It supports burst and single data access by the CPU. When the CPU request reading of 32-bit of data from the card, the host adapter performs multiple 8-bit or 16-bit read operation to collect 32-bit data for the CPU. When the CPU writes 32-bit data to the card, the host adapter performs multiple 8-bit or 16-bit write to the card to write all the data. Burst access is not supported by the host adapter. 

    Direct address mapping is provided by the host adapter with address space selected by chip select input signals. Customized address translation scheme can be provided upon customer request. 

    The Compactflash/PCMCIA host adapter operates on two clock domains, the user interface clock domain and the card interface clock domain. All I/O signals on the user interface are timed by the rising edge of the user interface clock. All I/O signals on the card interface are timed by the rising edge of the card interface clock. Request/Acknowledge and double synchronization are used when transfer data between the clock domains. This design approach allows the user interface to run at the higher CPU bus clock frequency while the card interface runs at a lower clock frequency.

    Features

    • Compliant with PC Card Standard 8.0, PCMCIA 2.1/JIEDA 4.2 and Compact-Flash 1.4
    • Allows host bus devices to access CompactFlash and PC Card/PCMCIA devices.
    • Simple user interface optimized for on-chip bus connection.
    • Dual clock design allows the user interface and the Card interface to operate at different clock domains.
    • User interface supports 32-bit and 64-bit data.
    • Option to integrate with other CPU bus slaves to support direct access by various CPU's including PowerPC, MPC860, ARM, SH2/3/4, MIPS, and ARC micro-processors.
    • Option to support 82365SL-compatible and EXCA register set.
    • In PC Card/PCMCIA mode, supports attribute memory access, common memory access and IO access.
    • In CompactFlash mode, supports attribute memory access, common memory access, IO access and IDE mode access.
    • Converts 64/32-bit CPU access to multiple 8-bit or 16-bit accesses.
    • Supports burst access by CPU. Burst access dispatched as multiple single accesses to the CompactFlash/PCMCIA interface.
    • Direct mapping of host address space to card address space.
    • CPU may operate at higher frequency while the card interface operates at lower frequency.
    • Designed for ASIC and FPGA implementations.
    • Fully static design with edge triggered flip-flops.

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    PCMCIA/CompactFlash Slave Controller

    The PCMCIA Card Slave is to be used inside a PCMCIA card. This module interface with the PCMCIA card signals on one side and a user interface on this other side. The PCMCIA card input is sampled by the local clk input and all interface to the user side are synchronous with the local clock. All PCMCIA request except some control register accesses are passed to the user interface. CIS structure is on the user side accessed through a dedicated port. Several control registers, COR, CSR, PRR and SCR are implemented in the design. Access to other registers are forwarded to the user side.

    Features

    • Functions as card interface on the card side.
    • Support PCMCIA and CompactFlash devices.
    • Operates asynchronously to the host devices in the other side of the card socket.
    • Synchronous interface to user logic in the card side.
    • Double synchronization of control signals.
    • Supports up to the highest speed devices.
    • Built-in control registers including COR, CS, PRR and SCR.
    • Supports CIS pointer structure defined by user.

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    Smart Card Interface Controller

    Smart card controller core is compliant to ISO 7816-3 specification. The core is a technology independent, fully synchronous design. The controller functions at 2 -66 Mhz.

    The design provides a simple, timing friendly front end interface which enables easy integration of the core to controllers and other application specific front end logic.

    The controller supports smart cards with internal clocks and internal resets .It has a well defined, easy to integrate processor interface. The design has hardware support for activation, deactivation and data transfer. It also supports hardware initiated smart card deactivation on card removal.

    Smart Card Controller IP is a cost-effective, end-to-end system validated solution that allows the licensees to easily migrate to FPGA, Gate array and Standard cell technologies optimally.

    Features

    • Supports asynchronous T = 0 and T =1 transmission protocols
    • Supports 2 -66 Mhz range for the input frequency
    • Supports class A, B and class AB smart cards
    • Timed interrupt for efficient support for synchronous protocol
    • Configurable depth for data path FIFO
    • Interrupts for all major events in hardware
    • Data filtering for signal integrity
    • C level driver for post integration SOC verification
    • Technology independent
    • Programmable timing parameters

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    ATA Host Controller

     

    Serial-ATA II Host Controller

    The SATA II IP core provides a full physical layer implementation of the 3.0 Gbps SATA standard. With full backwards compatibility to the 1st generation 1.5 Gbps data rate, the SATA IP core can be used to address any current SATA physical layer requirements. The SATA block features full support for generation and reception of spread spectrum modulated data up to 8000ppm. This spread spectrum clocking (SSC) support can improve the EMI performance of both computing and consumer applications. Additional features include programmable output swing, support for both slumber and partial power-saving modes, programmable out of band signaling thresholds.

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