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I2C Bus Controller
 
UART
 

CAN controller

 

SPI Interface

Advanced Switching Controllers

 

Rapid IO Controllers

 

SPI4.2 Controllers

Hyper Transport Controllers

 
Etc
   

I2C Bus Interface - Master

I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance between many devices. The core provides an interface between a microprocessor / microcontroller and an I2C bus. It can work as a master transmitter or master receiver depending on working mode determined by microprocessor/microcontroller. The core incorporates all features required by the latest I2C specification including clock synchronization, arbitration, multi-master systems and High-speed transmission mode. Built-in timer allows operation from a wide range of the clk frequencies.

Features

  • Conforms to v.2.1 of the I2C specification
  • Master operation
    • Master transmitter
    • Master receiver
  • Support for all transmission speeds
    • Standard (up to 100 kb/s)
    • Fast (up to 400 kb/s)
    • High Speed (up to 3,4 Mb/s)
  • Arbitration and clock synchronization
  • Support for multi-master systems
  • Support for both 7-bit and 10-bit address-ing formats on the I2C bus
  • Interrupt generation
  • Build-in 8-bit timer for data transfers speed adjusting
  • Host side interface dedicated for micro-processors/microcontrollers
  • User-defined timing (data setup, start setup, start hold, etc.)
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready

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I2C Bus Interface - Slave

I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance between many devices. The core provides an interface between a microprocessor/microcontroller and an I2C bus. It can works as a slave transmitter or slave receiver depending on working mode determined by a master device. The core incorporates all features required by the latest I2C specification including clock synchronization, arbitration and High-speed transmission mode. The Core supports all the transmission speed modes.

Features

  • Conforms to v.2.1 of the I2C specification
  • Slave operation
    • Slave transmitter
    • Slave receiver
  • Supports 3 transmission speed modes
    • Standard (up to 100 kb/s)
    • Fast (up to 400 kb/s)
    • High Speed (up to 3,4 Mb/s)
  • Allows operation from a wide range of input clock frequencies
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • Interrupt generation
  • User-defined data setup time
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready

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I2C Bus Interface Master/Slave

I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance between many devices. The core provides an interface between a microprocessor / microcontroller and an I2C bus. It can work as a master or slave transmitter/receiver depending on working mode determined by microprocessor/microcontroller. The core incorporates all features required by the latest I2C specification including clock synchronization, arbitration, multi-master systems and High-speed transmission mode. The Core supports all the transmission speed modes. Built-in timer allows operation from a wide range of the clk frequencies.

The Core is a technology independent VHDL or VERILOG design that can be implemented in a variety of process technologies and can be fully customized accordingly to customer needs.

Features

  • Conforms to v.2.1 of the I2C specification
  • Master mode
    • Master operation
      • Master transmitter
      • Master receiver
    • Support for all transmission speeds
      • Standard (up to 100 kb/s)
      • Fast (up to 400 kb/s)
      • High Speed (up to 3,4 Mb/s)
    • Arbitration and clock synchronization
    • Support for multi-master systems
    • Support for both 7-bit and 10-bit address-ing formats on the I2C bus
    • Build-in 8-bit timer for data transfers speed adjusting
  • Slave mode
    • Slave operation
      • Slave transmitter
      • Slave receiver
    • Supports 3 transmission speed modes
      • Standard (up to 100 kb/s)
      • Fast (up to 400 kb/s)
      • High Speed (up to 3,4 Mb/s)
    • Allows operation from a wide range of input clock frequencies
    • User-defined data setup time
  • User-defined timing (data setup, start setup, start hold, etc.)
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • Interrupt generation
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready

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Configurable UART

The Core is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C450. The Core performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). The Core includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. The Core has complete MODEM control capability, and a processor-interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link.

The Core includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.

D16450 is a technology independent design that can be implemented in a variety of process technologies.

The separate BAUD CLK line allows to set an exact transmission speed, while the UART internal logic is clocked with the CPU frequency.

The core is perfect for applications, where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for standalone implementation, where several UARTs are required to be implemented inside a single chip, and driven by some off-chip devices. Thanks to universal interface D16450 core implementation and verification are very simply, by eliminating a number of clock trees in complete system.

Features

  • Software compatible with 16450 UART
  • Configuration capability
  • Separate configurable BAUD clock linee
  • Majority Voting Logic
  • Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data
  • Independently controlled transmit, receive, line status, and data set interrupts
  • False start bit detection
  • 16 bit programmable baud generator
  • Independent receiver clock input
  • MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)
  • Fully programmable serial-interface characteristics:
    • 5-, 6-, 7-, or 8-bit characters
    • Even, odd, or no-parity bit generation and detection
    • 1-, 1½-, or 2-stop bit generation
    • Internal baud generator
  • Complete status reporting capabilities
  • Line break generation and detection. Internal diagnostic capabilities:
    • Loop-back controls for communications link fault isolation
    • Break, parity, overrun, framing error simula-tion
  • Full prioritized interrupt system controls
  • Fully synthesizable
  • Static synchronous design and no internal tri-states

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Configurable CAN Bus Controller

The DCAN is a stand-alone controller for the Controller Area Network (CAN) widely used in automotive and industrial applications. DCAN conforms to Bosch CAN 2.0B specification (2.0B Active). Core has simple CPU interface (8/16/32 bit configurable data width) with little or big endian adressing scheme. DCAN supports both standard (11 bit identifier) and extended (29 bit identifier) frames. Hardware message filtering and 64 byte receive FIFO enables back-to-back message reception with minimum CPU load. The DCAN is described at RTL level allowing target use in FPGA or ASIC technologies.

Features

  • Conforms to Bosch CAN 2.0B Active
  • 8/16/32-bit CPU slave interface with little or big endianess
  • Simple interface allows easy connection to CPU
  • Data rate up to 1 Mbps
  • Hardware message filtering (dual/single filter)
  • 64 byte receive FIFO
  • One transmit buffer
  • No overload frames are generated
  • Normal & Listen Only Mode
  • Single Shot transmission
  • Ability to abort transmission
  • Readable error counters
  • Last Error Code
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready

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Serial Peripheral Interface - Master/Slave

The Core is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. DSPI data are simultaneously transmitted and received. The Core is a technology independent design that can be implemented in a variety of process technologies. The Core system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or a slave device. Data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of eight different bit rates for the serial clock.

The Core automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS7O ? SS0O), and address SPI slave device to exchange serially shifted data. Error-detection logic is included to support interprocessor communications. A writecollision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode-fault detector automatically disables Core output drivers if more than one SPI devices simultaneously attempts to become bus master.

The Core is fully customizable, which means it is delivered in the exact configuration to meet usersí» requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.

Features

  • SPI Master
    • Master and Multi-master operations
    • 8 SPI slave select lines
    • System error detection
    • Mode fault error
    • Write collision error
    • Interrupt generation
    • Supports speeds up ¼ of system clock
    • Bit rates generated 1/4 - 1/512 of system clock.
    • Four transfer formats supported
    • Simple interface allows easy connection to microcontrollers
  • SPI Slave
    • Slave operation
    • System error detection
    • Interrupt generation
    • Supports speeds up ¼ of system clock
    • Simple interface allows easy connection to microcontrollers
    • Four transfer formats supported
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready

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Serial Peripheral Interface - Slave

The Core is a fully configurable SPI ma slave device, designated to operate with passive devices like memories, LCD drivers etc. The Core allows user to configure polarity and phase of serial clock signal SCK. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. The Core data are simultaneously transmitted and received. The Core system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. The Core allows the SPI Master to communicate with passive devices. When transmission starts (SS Line goes low) the first portion of data is copied to the address register and then to the ADDRESS bus output, after transmission of the address the Core generates the read signal (RD) and copy DATAI bus contents to the transmitter shift register, and prepare data to be exchanged with SPI Master. During the next data portion transmission Core simultaneously transmits data out and in. When the first data portion is received the Core asserts DATAO bus generates the write signal (WE), then increments ADDRESS bus performs a read operation and prepare another data portion to be exchanged with SPI master. Transmission is ended when the SS line goes high. The Core is a technology independent design that can be implemented in a variety of process technologies. The Core is fully customizable, which means it is delivered in the exact configuration to meet usersí» requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.

The Core is fully customizable, which means it is delivered in the exact configuration to meet usersí» requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.

Features

  • Full duplex synchronous serial data transfer
  • Slave operation
  • Automatic read and write operations
  • Automatic address incrementation after any data portion transfer
  • Configurable address and data length
  • Configurable SCK phase and polarity
  • Supports speeds up ¼ of system clock
  • Simple interface allows easy connection to passive devices, and SPI Master
  • Four transfer formats supported
  • Simple interface allows easy connection to microcontrollers
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready

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Advanced Switching (GPEX-AS)

GPEX-AS is a highly flexible and configurable end point controller IP targeted for both PCIExpress and Advanced Switching technology implementations in compute and communication applications. GPEX-AS is part of PCIExpress (GPEX) family of IP solutions, which includes End Point (GPEX-EP) and Root Complex (GPEX-RC) designs. GPEX-AS supports both PCI-Express and AS protocols. It supports PCI-express end-point and root complex functions, and AS port controller logic for a wide range of applications such as native AS node, leaf bridge, root bridge and switch. The controller architecture is tailored to address the needs of different market segments with highly configurable system PIs and support for PI-8, SLS, SQ and SDT. GPEX-AS architecture offers High performance, High link utilization, Low latency, Low power consumption and Small silicon footprint. It's simple, configurable, layered architecture is independent of application logic, PHY designs, implementation tools and the target technology.

Features

  • Compliant with AS Core Specification V1.0
  • Compliant with PCI-Express Base Specification V1.0a
  • Compliant with PI-8, SLS, SQ and SDT specification V1.0
  • Compliant with PIPE Architecture specification V1.0
  • Targets end-point, switch and bridge implementations
  • Optimally supports data rates ranging from 2G to 40G
  • Optimized for high link utilization and low latency
  • Supports up to 8 BVCs, 8 OVCs and 4 MVCs
  • Hardware assistance for system PI functions
  • Hardware assisted congestion management support
  • Efficient buffer management and flow control
  • Targets both FPGA and ASIC technologies

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Serial and Parallel (GRIO)

The RapidIO Interconnect Architecture, designed to be compatible with the most popular integrated communications processors, host processors, and networking digital signal processors, is a high-performance, packet-switched, interconnect technology. It addresses the high-performance embedded industry's need for reliability, increased bandwidth, and faster bus speeds in an intra-system interconnect. The RapidIO interconnect allows chip-to-chip and board-to-board communications at performance levels scaling to ten Gigabits per second and beyond. 

RapidIO controller core (GRIO) is designed to meet the growing needs of the industry. The core's simple, configurable and layered architecture is independent of applications, PHY designs, implementation tools and, most importantly, the target technology. The hardware and software configurable features make the core suitable for use in multiple applications. The design targets embedded systems, telecommunication, networking and any application where high speed, low latency response, low pin counts, reliability and scalability are necessary.

Features

  • Compliant with RapidIO specification, Revision 1.2
  • Supports both Serial and Parallel interfaces
  • Supports 1x and 4x serial interfaces at 1.25/2.5/3.125Gbps
  • Supports 8 and 16 bit parallel interfaces at 250/375/500 MHz
  • Implements physical, transport and logical layer functions
  • Supports both input/output and message passing protocols
  • Implements receiver controlled flow control
  • Supports all transaction flows and priorities
  • Support for up to 256 bytes data payload
  • Supports 34 bit addressing
  • Implements a flexible buffer management scheme
  • Performs link initialization, training, error detection and recovery
  • Performs auto detection of interface widths and modes
  • Targets FPGA, Structured ASIC and Standard Cell technologies
  • Supports Multi-cast event control symbols

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SPI4.2 (GSPI4.2-MC)

SPI-4 Phase 2 is an interface defined for packet or cell transfer between physical layer device and link layer device, for aggregate bandwidth of OC-192 ATM, Packet over SONET/SDH, and 10 Gbps Ethernet applications.  

SPI4P2 Interface controller is a highly configurable and efficient implementation, fully compliant to Optical Internet working forum's OIF-SPI4-02.0, System packet level interface Level 4 Phase 2 implementation agreement. SPI4P2 is a fully digital, multi-module design created to provide complete solution in variety of application scenarios: from dynamic alignment through protocol and FIFO management.  

The core's simple, configurable and layered architecture is independent of applications, PHY designs, implementation tools and, most importantly, target technologies. SPI4P2 Interface Controller is a cost-effective, end-to-end system validated solution that allows the licensees to easily migrate to FPGA, Gate array and Standard cell technologies optimally.

Features

  • Compliant to OIF-SPI4-02.0, OIF's SPI-4.2 implementation agreement
  • Modular structure with optional digital serdes and FIFO
  • manager blocks.
  • Supports 64 or 128 bit user logic interface.
  • Supports single and multi link operations - scalable from 1 to 256 links
  • Supports "LVTTL" or "LVDS" or "LVTTL&LVDS" signaling for status path.
  • Supports micro level de-skew and bit level de-skew on the receive paths.
  • Single user logic interface or multiple user logic interfaces.
  • Interrupt generation for reserved control words, DIP4 error, SOP error, EOP error.
  • Bandwidth optimized design using shared sop-eop control word without filling idle control words.
  • Supports flexible FIFO schemes

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SPI4.2 to XAUI Bridge

Features

  • Integrates 10G Ethernet MAC with SPI4.2
  • Bridges transparently XAUI to SPI4.2
  • FIFOs with programmable thresholds

Interfaces :

  • SPI4.2
  • XGMII
  • XAUI

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Cave (GHT-Cave)

HyperTransport technology is a highspeed, low-latency, point-to-point link for interconnecting integrated circuits (ICs) on a board. It is a packet-based link implemented on two independent unidirectional sets of wires. HyperTransport Cave is an endpoint device in the HyperTransport chain. HyperTransport Cave core is designed for reuse and its flexible backend interface makes it easy to be integrated into wide range of applications. The core provides highly scalable bandwidth through programmable link widths and frequencies

Features

  • Compliant with HyperTransport I/O Link Specification, Ver. 1.03
  • Can be hardware configured for 16-bit or 8-bit link interface
  • Supports software programmable link widths of 16, 8, 4, or 2 bits
  • Supports 800, 600, 500, 400, or 200 MHz link frequency
  • Maximum bandwidth is 6.4 Gb/sec
  • Supports link disconnect protocol
  • Supports interrupt
  • Supports external and internal loop backs
  • Optional transaction interface provides target and initiator interfaces
  • Optional packet interface for network applications

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Host (GHT-Host)

HyperTransport technology is a highspeed, low-latency, point-to-point link for interconnecting integrated circuits (ICs) on a board. It is a packet-based link implemented on two independent unidirectional sets of wires. HyperTransport Host is the root of the HyperTransport fabric. HyperTransport Host core is designed for reuse and its flexible backend interface makes it easy to be integrated into wide range of applications. The core provides highly scalable bandwidth through programmable link widths and frequencies.

Features

  • Compliant with HyperTransport I/O Link Specification, Ver. 1.03
  • Can be hardware configured for 16-bit or 8-bit link Interface
  • Supports software programmable link widths of 16,8, 4 or 2 bits
  • Supports 800, 600, 500, 400, or 200 MHz link Frequency
  • Maximum bandwidth is 6.4 Gb/sec
  • Supports double-hosted chain
  • Supports link disconnect protocol
  • Supports peer-to-peer transactions
  • Supports reset generation
  • Supports interrupt
  • Supports external and internal loop backs
  • Optional transaction interface provides target and initiator interfaces
  • Optional packet interface for network applications

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Tunnel (GHT-Tunnel)

HyperTransport technology is a highspeed, low-latency, point-to-point link for interconnecting integrated circuits (ICs) on a board. It is a packet-based link implemented on two independent unidirectional sets of wires. HyperTransport tunnel is a popular topology with dual HyperTransport links which allows daisy chaining of tunnel devices to create an IO channel, connecting multiple I/O devices to a host system. HyperTransport Tunnel core, is designed for reuse and it's flexible backend interface makes it easy to be integrated into wide range of applications. The core provides highly scalable upstream and downstream bandwidths through programmable link widths and frequencies.

Features

  • Proven design compliant with HyperTransport I/ O Link Specification, Version 1.03
  • Provides dual HyperTransport links
  • Either link can be hardware configured for 16- bit or 8- bit link interface
  • Either link supports software programmable link widths of 16, 8, 4, or 2bits.
  • Either link can be configured as upstream Either link supports 800, 600, 500, 400, or 200 MHz Link frequency
  • Maximum bandwidth is 6.4 GB/sec on both links
  • Supports independent link width and frequency for each link
  • Supports link disconnect protocol
  • Supports interrupt.
  • Supports external and internal loop backs on both HyperTransport links
  • Optional transaction interface provides target and initiator interfaces Optional packet interface for network applications

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HDLC

HDLC Controller is a single-channel HDLC controller core. The device contains a full-duplex transceiver with independent transmit and receive sections for bit-level HDLC protocol operations.

The core is designed for easy integration into wide range of applications implemented on most ASIC and FPGA technologies. The interface of this core can be adapted for a wide range of FIFO controllers.

Features

  • Flag insertion and detection
  • Abort generation and detection.
  • Zero bit stuffing and deletion
  • 16-bit CRC-CCITT generation and checking.
  • CRC can be separately enabled and disabled for transmit.
  • Automatic insertion of 1 to 255 IDLE Characters between frames.
  • Enable and data valid signals for flow control.
  • Operates up to 155.52Mbit/s (STS-3) data rates.
  • Full-duplex operation.

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T1/E1 Framer

The T1/E1 framer multiplexes the PCM data, signaling data and data link data onto the T1/E1 line. The deframer de-assembles the PCM data, signaling data and data link data from the serial data received on the T1/E1 line. Alarms are generated at the de- assembler in accordance with the ITU-T recommendations.

In Framer, a serial interface is provided to the T1/E1 line for receiving the serial data output of the Framer. In De-Framer, the De-Framer provides a serial interface to the T1/E1 line, and the serial T1/E1 framed data is clocked into the de-framer from the line.

T1/E1 Framer works as per the ITU-T G.704 standard. The multiplexed data has to be clocked to the T1/E1 lines at the T1/E1 clock rates. The function of the de-framer is to re-synchronize with the start of the frame and extract the data link, signalling, CRC, PCM data from the received serial bit stream or to loose synchronization as per ITU-T G.706 standard.

Features

  • Conforms to ITU-T recommendations, G.704, G.706and G.775
  • Fully independent framer and de-framer with feedback to framer from de-framer
  • T1 framer supports SF and ESF framing formats
  • Supports ABCD signaling in T1-ESF mode, AB signaling in T1-SF mode and channel associated signaling in E1 mode
  • Provides two frame/four frame controlled slip buffers with parameterized threshold for repeating and deleting frames.
  • Fully synchronous design using multiple clocks, with asynchronous reset synchronized for different clocks
  • Supports CRC in T1-ESF and E1 framer/de-framer.
  • Provides detection of Blue Alarm (AIS) and Red alarm (Loss of synchronization by de-framer)
  • Indicates occurrence of CRC errors, framing bit errors and controlled slips.
  • Automatic internetworking between CRC-4 and non CRC-4 interfaces for E1 framer and de-framer as specified in ITU-T G.706 recommendation

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