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I2S Controller

I2S Controller is a highly configurable core for use in I2S compliant CODECs. It provides a simple glueless interface to industry standard audio devices. This digital audio controller core is compliant to the dominant audio standard protocol I2S. The core is optimally architected for high performance, low latency and small silicon footprint.

The core is provided with the generic processor bus interface on the system side enabling the core to be used in a variety of applications including SoC applications. The core's simple and configurable architecture is independent of implementation tools and, most importantly, target technologies. I2S core is a cost-effective, end-to-end solution that allows the licensees to easily migrate to FPGA, Gate array and Standard cell technologies optimally.

Features

  • Compliant to I2S Serial Bus protocol
  • Supports full duplex flow control - 1 PCM playback channel and 1 record channel l
  • Supports 8/16/18/20/24/32 bit DAC/ADC resolution
  • through software configuration
  • Supports both 256 and 384 sampling frequency (fs)
  • operating mode
  • Support 8/16/32/48/96/192/44.
  • 1/88.2/176.4KHz audio sample frequency
  • Processor Bus 8/16/32-bit wide Interface on system side
  • Supports 1/2/4 samples per 32 bit packing option through software configuration
  • Fully synchronous design with serial clock and system clock
  • Interrupt Support for FIFO data read/write
  • Programmable FIFO thresholds
  • Loop back mode for testing purposes

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Configurable Digital Audio Serial Input

The IP core is a configurable stereo audio interface component designed to input a serial digital audio stream. The Core supports the well known I2S interface format originally developed by Philips and also the Left-Justified or Right-Justified serial audio formats. The Core can be configured at runtime to support two(16, 20, 24 or 32 bit) audio channels read from two different addresses in an interleaved manner, or two 16-bit audio channels read in parallel from the same register.

Features

  • Configurable input format: I2S, Left Justified or Right justified (chosen at runtime)
  • Configurable sample FIFO depth (at pre-synthesis time).
  • Supports user configurable sample width (at runtime).
  • Reports number of samples in FIFO.
  • Reports FIFO empty, full, almost empty and almost full condition.
  • Runtime Configurable Upper-FIFO-Limit; a request is activated when this limit is exceeded.
  • Supports up to 32 bits per sample.
  • Supports all commonly used sample rates including 32, 44.1, 48, 96, 192 and 384 kHz.
  • Runtime Configurable read method. Serial sample read (Left and then Right), or parallel sample read (Left and Right).
  • Flexible CW-Link interface, which permits bridging to standard interfaces (I2S, IBM CoreConnectTM, AMBATM AHB, etc).

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Configurable Digital Audio Serial Output

The IP core is a configurable stereo audio interface component designed to output a serial digital audio stream. The Core supports the well known I2S interface format originally developed by Philips and also the Left-Justified or Right-Justified serial audio formats. The Core can also be configured at runtime to support two (16, 20, 24 or 32 bit) audio channels written to two different addresses in an interleaved manner (¡°dualchannel-interleaving¡±), two 16-bit audio channels read in parallel from the same register address (¡°parallel-dualchannel write mode¡±), or one (16, 20, 24 or 32 bit) audio channel ¡°single-channel¡± write mode.
The audio samples are placed into a transmission FIFO using the CW-Link format. A runtime configurable output stage retrieves the samples from the FIFO and serializes the data to generate the serial audio stream (I2S, Left-Justified, or Right-Justified). The FIFO input is clocked with the bus clock (cw_clk) unrelated to Fs (it must be clocked at a frequency above 2xFs when in dual-channel-interleaving mode, or above Fs for parallel-dualchannels or single-channel write), and the FIFO output is clocked with the serial audio master clock (mclk) at a
frequency of 256xFs, where Fs is the sample rate frequency.

Features

  • Configurable output format: I2S, Left Justified, Right Justified (chosen at run time).
  • Configurable sample FIFO depth (at pre-synthesis time).
  • Supports user configurable sample width (at run time).
  • Reports number of samples in FIFO.
  • Runtime Configurable Lower-FIFO-Limit; a request is activated when this limit is exceeded
  • Reports FIFO empty, full, almost empty and almost full condition.
  • Supports up to 32 bits per sample.
  • Supports all commonly used sample rates including 32, 44.1, 48, 96, 192 and 384 kHz.
  • Configurable sample write method. Serial sample write (Left and then Right), or parallel sample write (Left and Right).
  • Flexible CW-Link interface, which permits bridging to standard interfaces (I2S, IBM CoreConnectTM, AMBATM, etc).

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I2S to SPDIF-AES/EBU Converter

The Core is a digital audio transmitter IP core implementing the SPDIF, AES/EBU, AES3 or IEC60958 standards. The Core inputs the well known I2S format, popular in many data converters. It also allows customizing the SPDIF-AES/EBU control bits according to user applications.

Features

  • Supports the IEC60598 (SPDIF, AES3, AES/EBU) and I2S standards.
  • Supports sample rates up to frequency mclk/256 (384KHz for mclk = 98MHz).
  • Supports up to 24 bits per sample.
  • User defined SPDIF-AES/EBU control bits can be inserted in the SPDIF-AES/EBU signal.
  • Low power mode when idle.

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SPDIF-AES/EBU to I2S Converter

The Core is a digital audio receiver IP core implementing the SPDIF, AES/EBU, AES3 or IEC60958 standards. The Core inputs an SPDIF signal and samples it with a fast clock to extract the clock, audio and control data from it. It outputs PCM audio data in the well known I2S format, popular in many data converters. 

Features

  • Feed-forward operation: extracts audio data from the SPDIF-AES/EBU input signal by sampling it with a fast clock signal, not necessarily related to the sample rate frequency.
  • The audio samples are output serially in I2S format.
  • PLL interface to filter out the jitter and generate a jitter-free I2S output.
  • Typical applications: digital audio, video (DVD), and multimedia systems in general.

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Configurable SPDIF-AES/EBU Receiver

The Core Configurable SPDIF-AES/EBU Receiver is a digital audio receiver IP core supporting the SPDIF, AES/EBU, AES3 and IEC60958 standards and also the IEC61937 and SMPTE 337M standards for non-PCM audio. The Core receiver is able to extract the data from the SPDIF input using a fast clock whose frequency need not be related to the sample rate frequency Fs. This feature is useful in systems where a clock 540X or faster than Fs is available, for example in most DVD players such a clock is already available. It can extract up to eight independent time multiplexed streams from the incoming SPDIF signal when receiving non-PCM audio. The Modular structure of CWda14 allows enhanced performance for specific applications by using (not using) the optional Add-on-Modules (AOM).

Features

  • Supports any sample rates up to frequency cw_clk/540 including 32, 44.1, 48, 96 and 192 kHz.
  • Measures input sample rate.
  • Lock time less than 3 sub-frames.
  • Reduced bandwidth by automatic removal of stuffing bits in non-PCM mode.
  • Outputs jittery sample bit clock (average frequency 64xFs).
  • Sample bit clock jitter can be attenuated with a 2nd order 100KHz cutoff frequency PLL to produce a good quality retransmission clock.
  • Flexible Coreworks Link interface, which permits bridging to standard interfaces (I2S, IBM CoreConnect¢â, AMBA¢â, etc).
  • Separate interfaces for data and control.
  • Modular Structure using optional Add-on-Modules (AOM).
  • Channel Status and User Data memory mapped buffers with programmable masks for change notification.
  • Configurable audio data FIFO reporting the number of samples in FIFO and programmable almost full condition that can accessed trough the data CW-Link.
  • I2S output interface that can be clocked using an internally extracted jittery clock, or an external jitter free clock that can be generated from the bitclk with a PLL.

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Configurable SPDIF-AES/EBU Transmitter

The Configurable SPDIF-AES/EBU Transmitter is a digital audio transmitter IP core supporting the SPDIF IEC60958, AES/EBU and AES3 standard and also the IEC61937 and SMPTE 337M for non-PCM audio. When transmitting PCM audio, the user must ensure the availability of data in the FIFO. If the FIFO gets empty, silencing SPDIF frames marked as invalid are sent are until the arrival of new audio data. When transmitting Non-PCM bursts, the Core will optionally fill the SPDIF sub-frames with zeros until the next burst, if the repetition periods for the data burst and the pause burst are provided. When the FIFO is empty, the Core sends bit stuffing and periodic NULL Data Bursts according to the Non-PCM IEC61937 standard. The Modular structure of Core allows enhanced performance for specific applications by using (not using) the optional Add-on-Modules (AOM).

Features

  • Supports the IEC60958 (SPDIF), AES3, AES/EBU standards for PCM audio transmission.
  • Supports the IEC61937, SMPTE 337M standards for non-PCM audio transmission.
  • Supports any sample rates up to frequency mclk/256 including 32, 44.1, 48, 96 and 192 kHz.
  • Reduced bandwidth by automatic insertion of stuffing bits in non-PCM mode.
  • Automatic insertion of Validity bits in non-PCM mode.
  • Flexible CW-Link interface, which permits bridging to standard interfaces (IBM CoreConnect¢â, AMBA¢â, etc).
  • Separate interfaces for data and control.
  • Modular Structure using optional Add-on-Modules (AOMs).
  • Channel Status and User Data memory mapped buffers.
  • Configurable audio data FIFO, reporting number of samples in FIFO and programmable almost empty condition.
  • I2S input interface, which permits direct interface with most audio ADCs and other audio devices.

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Low Cost Audio Sample Rate Converter

The Core is a low cost configurable Mono/Stereo asynchronous Audio Sample Rate Converter (ASRC). This core can be used to solve the problem of interfacing digital audio equipment operating at different sample rates. It has been designed for systems requiring moderate quality in terms of harmonic distortion and noise: it can realize most common sample rate conversions  at -70 dB of Total Harmonic Distortion plus Noise (THD+N), while requiring very few logic resources.

Features

  • Supports the IEC60958 (SPDIF), AES3, AES/EBU standards for PCM audio transmission.
  • Supports the IEC61937, SMPTE 337M standards for non-PCM audio transmission.
  • Purely digital solution for clock and data recovery requiring a system clock cw_clk unrelated to oksampling rate Fs.
  • Converts between asynchronous sample rates
  • Stereo (CWda50s) and Mono (CWda50m) versions.
  • -70dB THD+N for common conversion rates.
  • 83 dB Dynamic Range for common conversion rates.
  • Fully digital solution.
  • 14-bit resolution.
  • Flexible Coreworks Audio Parallel Interface (CWAPI) at the input and output, which permits bridging to other standard interfaces (IBM CoreConnectTM, AMBATM, I2S and AES-EBU/SPDIF).
  • Additional I2S slave audio interface.
  • Very low use of logic resources.
  • Converts between low sample rates in the 8-12KHz range on low cost FPGAs.
  • Converts between any common sample rates on ASICs.
  • Low power mode when idle.

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Multi-Channel Audio Sample Rate Converter

The Core is a Multi-channel Asynchronous Audio Sample Rate Converter (ASRC). This core can be used to interface digital audio equipment operating at different sample rates. It has been designed for systems requiring very high quality in terms of harmonic distortion and noise: it can realize most common sample rate conversions with less than -120 dB of Total Harmonic Distortion plus Noise (THD+N), having also a Dynamic range of 131 dB. The Core uses the Coreworks Audio Parallel Interface (CWAPI) for the input and output audio data, which permits bridging to other interfaces: I2S, SPDIF-AES/EBU, AMBA, PowerPC (CoreConnect).

Features

  • Converts between asynchronous sample rates
  • Multi-channel audio, configurable up to 8 channels
  • Lower than -120 dB THD+N for common conversion rates
  • Greater than 131 dB Dynamic Range for common conversion rates
  • Fully digital solution
  • Flexible Coreworks Audio Parallel Interface (CWAPI) at the input and output, which permits bridging to other standard interfaces (IBM CoreConnect¢â, AMBA¢â, I2S and AES-EBU/SPDIF)
  • Input and output sample rate range: 8kHz to 96kHz
  • Sampling rate conversion ratios from 7:1 to 1:7

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SDI Audio De-embedder

The Core implements an ancillary data packet de-embedder for SDI. It is able to extract the contents of one audio group (4 channels). This implementation is restricted to 20 audio bits per sample, hence the extended data structure described in the ANSI/SMPTE 272M standard (data extension to support 24 audio bits per sample) is not implemented in the present version.

The Core uses two clocks. All input signals are sampled in the rising edge of the video clock signal. This clock is extracted from the incoming SDI bitstream. The other clock, audio clock, is used to output the audio samples. The audio clock frequency must be 256xFs (sample frequency). The video and audio clocks must be derived from the same source.

The audio samples are output using the Coreworks CW_LINK format. When present, AES auxiliary information is extracted from the ancillary packets. This information includes the Validity, Channel Status, and User bits. The block_start signal is asserted high every 192 audio frames.

Features

  • Supports the ANSI/SMPTE 272M standard.
  • Supports 20 bits of audio data.
  • Supports sample rates that bear a rational relationship to the video clock (most common is 48 kHz).
  • Extracts audio control bits from the incoming ancillary data.
  • Extracts all active channels in the selected audio group (up to 4 audio channels).

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SDI Audio Embedder

The Core implements an ancillary data packet embedder for SDI. It is able to insert the contents of one audio group (4 channels). This implementation is restricted to 20 audio bits per sample, hence the extended data structure described in the ANSI/SMPTE 272M standard (data extension to support 24 audio bits per sample) is not implemented in the present version.
The Core uses two clocks. All input signals are sampled on the rising edge of the audio clock signal. The other clock, video clock, is used to output the auxiliary data. The video and audio clocks must be derived from the same source.
The audio samples inputs use the CW_LINK format. AES auxiliary information is also inserted in the ancillary packets. This information includes the Validity, Channel Status, and User bits.

Features

  • Supports the ANSI/SMPTE 272M standard
  • Supports 20 bits of audio data
  • Supports sample rates that bear a rational relationship to the video clock (most common is 48 kHz)
  • Extracts ancillary control bits from the incoming cw_link signal
  • Supports all active channels in the selected audio group (up to 4 audio channels)

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